In a typical dicing process of a semiconductor wafer (dicing target) for separating plural semiconductor chips from the semiconductor wafer, an annular blade having, for example, diamond particles adhered thereto is rotated at high speed and makes contact upon a scribe line formed on the semiconductor wafer. By the rotating blade making contact upon the scribe line, the semiconductor wafer is diced into plural semiconductor chips. In order to achieve better dicing performance, various parameters are optimized. The parameters include, for example, the thickness of the blade, the rotational speed of the blade, the stage speed, and the depth of the cut.
The semiconductor wafer has a layered configuration with various thin films formed on a silicon substrate and is not formed with a uniform material with respect to the thickness direction of the semiconductor wafer. More specifically, the semiconductor wafer includes metal wiring that is formed of a metal material mainly comprising aluminum material (widely used as wiring of semiconductor chips). The material of the metal wiring has a characteristic different from that of the silicon material of the silicon substrate.
Furthermore, the semiconductor wafer has a process-monitor provided on a scribe line of the semiconductor wafer for inspecting the performance of the semiconductor chips of the semiconductor wafer. The process-monitor includes a process-monitor electrode pad for evaluating the electrical characteristics of a process-monitored semiconductor device. The process-monitoring pad is also formed of a metal material. Therefore, in a process of dicing the semiconductor wafer, a layered configuration including a silicon substrate, an insulation film, and a metal material is diced.
FIGS. 15A and 15B are diagrams for showing the vicinity of a scribe line of a conventional semiconductor wafer. FIG. 15A is a plan view of the conventional semiconductor wafer. FIG. 15B is a cross-sectional view taken along line W-W of FIG. 15A.
A LOCOS (Local Oxidation of Silicon) oxide film 17 is formed on a semiconductor substrate 15. A BPSG (Boro-Phospho silicate glass) film 19 is formed on the LOCOS oxide film 17.
A first metal wiring layer 21-1 is formed on the BPSG film 19. The first metal wiring layer 21-1 is situated in the area where a process-monitor electrode pad 31 is formed. Furthermore, in the area illustrated in the drawing, the first metal wiring layer 21-1 is formed in an annular shape along a peripheral part of the semiconductor chip 3.
A first interlayer insulation film 23-1 is formed on the BPSG film 19 and also on the first metal wiring layer 21-1. A through-hole is formed in the first interlayer insulation film 23-1 on the first metal wiring layer 21-1 in the area where the process-monitor electrode pad 31 is formed. Furthermore, an annular through-hole is formed in the first interlayer insulation film 23-1 on the first metal wiring layer 21-1 along a peripheral part of the semiconductor chip 3.
A second metal wiring layer 21-2 is formed on the first interlayer insulation film 23-1. The second metal wiring layer 21-2 is situated in the area where the process-monitor electrode pad 31 is formed and in the through-hole thereof. Furthermore, in the area illustrated in the drawing, the second metal wiring layer 21-2 is formed in an annular shape along a peripheral part of the semiconductor chip 3.
A second interlayer insulation film 23-2 is formed on the first interlayer insulation film 23-1 and also on the second metal wiring layer 21-2. A through-hole is formed in the second interlayer insulation film 23-2 on the second metal wiring layer 21-2 in the area where the process-monitor electrode pad 31 is formed. Furthermore, an annular through-hole is formed in the second interlayer insulation film 23-2 on the second metal wiring layer 21-2 along a peripheral part of the semiconductor chip 3.
A third metal wiring layer 21-3 is formed on the second interlayer insulation film 23-2. The third metal wiring layer 21-3 is situated on the second interlayer insulation film 23-2 of the area where the process-monitor electrode pad 31 is formed and in the through-hole thereof. Furthermore, in the area illustrated in the drawing, the third metal wiring layer 21-3 is formed in an annular shape on the second interlayer insulation film 23-2 and in the through-hole along a peripheral part of the semiconductor chip 3.
A final protective layer 25 is formed on the second interlayer insulation film 23-2 and on the third metal wiring layer 21-3. A pad opening part is formed in the final protective layer 25 in the area where the process-monitor electrode pad 31 is formed. Thereby, the surface of the third metal wiring layer 21-3 is in an exposed state.
The above-described metal wiring layers 21-1, 21-2, and 21-3 situated in the vicinity of the peripheral part of the semiconductor chip 3 together form a guard ring 21.
In a dicing process, it is generally difficult to dice (cut) plural films formed of different materials at a single time and the dicing tends to lead to a problem of the creation of metal burrs. Normally, since a process-monitor semiconductor device situated in a dicing line is relatively small in size, the process-monitor semiconductor device can be thoroughly diced without any metal burr in a case where, for example, a blade having a thickness of 20-50 μm is employed. Meanwhile, since a process-monitor electrode pad has a width of at least 60 μm or more, the width of the process-monitor electrode pad will be greater than the thickness of such blade (width of the dicing area). This results in the problem of metal burrs.
This problem could be overcome by making adjustments in the dicing process in a case of employing a design rule referred to as a half-micron process which is applied to two-three wiring layers.
However, in recent years and continuing, there is a significant increase in forming multiple layers of metal wiring since semiconductor devices are fabricated in finer sizes (for example, fabricating a semiconductor device having seven-eight wiring layers is not unusual). Accordingly, in a case where plural layers of metal wiring are provided as a process-monitor electrode pad on a scribe line, the metal film(s) included in the process-monitor electrode pad causes metal burrs.
Furthermore, in recent years and continuing, various methods of planarization technology of an insulation film are used for solving the problem of focus depth in a case of using photolithography technology. The method of planarizing the surface of an insulation film may be, for example, using a CMP (Chemical Mechanical Polishing) method, or employing a BPSG film as the film between a polysilicon layer and a metal layer. The BPSG film, which is an insulation film formed by including boron and phosphorous into a silicon oxide layer, is fabricated by employing a CVD (Chemical Vapor Deposition) method. By increasing the concentration of boron and/or phosphorous, the surface of the insulation film can be suitably planarized. Therefore, the concentration of boron and/or phosphorous is increased to reduce the size of semiconductor devices.
However, the inventor of the present invention found that the adhesion between the BPSG film and the metal wiring layer (more specifically, between the BPSG film and a titanium film serving as a substrate of an aluminum alloy and having a high melting point) becomes weaker as the concentration of boron and/or phosphorous in the BPSG film is increased. This is because the increase in the concentration of boron and/or phosphorous not only promotes planarization, but at the same time, reduces the micro-roughness of the BPSG film. This results in loss of contact area between the BPSG film and the metal film. Therefore, the finer the semiconductor device is fabricated by increasing the concentration of boron and/or phosphorous, the more likely that metal burring of the process-monitor electrode pad occurs in the dicing process. As a result, dicing of semiconductor wafers becomes more difficult.
One example for preventing such a problem is disclosed in Japanese Laid-Open Patent Application No. 2005-191334. Japanese Laid-Open Patent Application No. 2005-191334 discloses a process-monitor electrode pad disposed inside a semiconductor chip so that only the semiconductor device for process monitoring is disposed on the scribe line. Accordingly, the electrode pad would not obstruct the dicing process.
However, since the method disposes a process-monitor electrode pad inside a semiconductor chip, the semiconductor chip is to be formed in a large size. This increases manufacturing cost. This additional electrode pad disposed inside the semiconductor chip is a critical problem particularly for a semiconductor chip product having a large number of electrode pads, since the chip size of the product is decided according to the limits in the distance between electrode pads.
As shown in FIG. 15B, a guard ring formed of a metal material may be disposed between a semiconductor chip and a scribe line for preventing the inside of the semiconductor chip being damaged in the dicing process. However, by disposing the process-monitor electrode pad inside the semiconductor chip, the process-monitor electrode pad is required to overstep the guard ring for contacting with a process-monitor semiconductor device. This is a difficult task to accomplish since a portion of the guard ring, being formed of metal material, would undesirably be cut off for accomplishing such task. If such portion of the guard ring is cut off, the purpose of providing the guard ring would be lost.
Japanese Laid-Open Patent Application No. 2005-191334 also discloses an example of disposing a process-monitor electrode pad inside a semiconductor chip and using the process-monitor electrode pad not only for process-monitoring but also as an electrode pad of the semiconductor chip.
However, since there is, in general, no correlation between the number of semiconductor devices provided on the scribe line for process-monitoring and the number of electrode pads used in each product, it is difficult to adjust the position of semiconductor devices disposed on the scribe line and the position of the electrode pads used for a product. Furthermore, this example requires a separate probe card for each product when performing electric measuring with a process monitoring device. In addition, this example does not resolve the above-described problem of the guard ring.
Japanese Laid-Open Patent Application No. 2005-191334 also discloses an example of disposing process-monitor electrode pads and semiconductor devices within the scribe line but not in the dicing area (cutting area) of the scribe line.
However, this example requires the scribe line to be wide. This reduces the number of semiconductor chips that can be cut off (diced) from a semiconductor wafer. As a result, manufacturing cost is increased.